1). Field of the Invention
This invention relates to a silicon wafer testing rig, and to a method of testing an integrated circuit in a silicon wafer when the wafer is bent.
2). Discussion of Related Art
FIG. 1 of the accompanying drawings illustrates a conventional semiconductor package 10 which includes a package substrate 11 and an integrated circuit 12 which is mounted on the package substrate 11 by an array of solder balls 13. A circuit 14 is located in a surface of the semiconductor chip 12 facing the package substrate 11. Electrical leads (not shown) extend through the package substrate 11 and terminate at bond pads (not shown) on a surface of the package substrate 11 opposing the integrated circuit 12.
The semiconductor package 10 is mounted to a mother board or a card for a computer with the bond pads, referred to, making contact with the motherboard or the card.
FIG. 2 illustrates schematically a transistor 15 which typically exists in the circuit 14. The transistor 15 includes first and second spaced doped regions 16, and a gate 17. A voltage is applied over the doped regions 16. When a voltage is applied to the gate 17, electrons are caused to move between the doped regions 16.
The package substrate 11 is typically made of an organic material with a relatively high coefficient of thermal expansion and the semiconductor chip 12 is typically made of silicon with a relatively low coefficient of thermal expansion. In order to bond the solder balls 13 to the package substrate 11, the semiconductor package 10 is sent through a furnace at an elevated temperature so as to cause reflow of the solder balls 13. The semiconductor package 10 is then removed from the furnace. Once the semiconductor package 10 is removed from the furnace and the integrated circuit 12 and the package substrate 11 are allowed to cool to room temperature, the package substrate 11 tends to shrink more than the integrated circuit 12 due to its higher coefficient of thermal expansion. FIG. 3 illustrates in exaggerated detail how the package substrate 11 and the integrated circuit 12 deform due to differences in thermal expansion coefficients. Both the package substrate and the integrated circuit 12 are deformed into dome shapes. A surface of the integrated circuit 12 in which the integrated circuit 14 is located is thereby placed under compressive stress.
Stresses in the integrated circuit 14 have an effect on the electrical characteristics of the transistor 15. In particular, the movement of the electrons between the doped regions 16 increases or decreases when the transistor 15 is stressed due to changes in the carrier mobility of the material between the doped regions 16.
For proper chip design it is often necessary to know what kind of stresses exists in the integrated circuit and what the effects of these stresses are on the circuit 14. These stresses may be simulated by bending a wafer which contains an integrated circuit, and contacting the integrated circuit with a probe card. The probe card may be connected to an electrical tester. The electrical tester may then be used for testing characteristics of the integrated circuit in the bent wafer. The wafer may be bent into a channel shape which would cause stresses in the integrated circuit. However, as previously discussed, an integrated circuit tends to bend into a dome shape. By bending the wafer into a channel shape would therefore not accurately simulate the stresses within an integrated circuit.